1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory with a FUSI (Full Silicide) structure in which an entirety of a control gate electrode is silicided.
2. Description of the Related Art
In a nonvolatile semiconductor memory having a memory cell with a stack gate structure, for instance, a NAND type flash memory, when the memory cell is shrunk and its gate length becomes in 50 nm or less, floating gate electrodes of the two memory cells adjacent to each other interfere, so that various problems occur (for instance, refer to Jpn. Pat. Appln. KOKAI Publication No. 2003-60092).
For instance, in the case of the cell structure in which a control gate electrode (word line) covers a side surface of the floating gate electrode, when part of the control gate electrode, that is, part between the floating gate electrodes is depleted due to miniaturization of the memory cell, the part does not function as the gate electrode, so that coupling ratio deteriorates.
In addition, since parasitic capacitance generated between the two control gate electrodes (word line) adjacent to each other becomes large, signal speed slows, resulting in cause of increase in write/read time.
In order to solve such problem, there has been proposed a FUSI (Full Silicide) structure in which an entirety of the control gate electrode is silicided.
According to the memory cell with the FUSI (Full Silicide) structure, part of the control gate electrode is not depleted; and in addition, since the silicide itself is in low resistance, signal delay is alleviated.
However, there is a problem in the FUSI (Full Silicide) structure. In case of employing this structure, the problem is that fluctuation of property of FET (Field Effect Transistor) formed simultaneously with a memory cell becomes large.
Specifically, the FET (a selection transistor in a cell array, transistors constituting a peripheral circuit) formed simultaneously with the memory cell, like the memory cell, has a stack gate structure. However, two gate electrodes are electrically connected to each other via an inter-gate insulating film, that is, via an opening provided at IPD (Inter-Polysilicon Dielectric).
In this case, when siliciding an entirety of an upper gate electrode of the FET at the same time as the control gate electrode is silicided, metal atoms are diffused in a lower gate electrode via the opening provided on the inter-gate insulating film; and then part of the lower gate electrode is also silicided.
Then, in the case where silicide formation of the lower gate electrode advances to a neighboring area to a gate insulating film, the structure results in a state that part in which the silicide comes into contact with the gate insulating film, and part in which conductive polysilicon neighbors the gate insulating film are mixed.
Since a flatband voltage to a silicon substrate of the silicide is different from that of the conductive polysilicon, there occurs a problem that threshold of FET fluctuates depending on state of progress of the silicide formation of the lower gate electrode.